Abstract: We introduce a deep learning-based optimization method that enhances the design of sparse phased array by reducing grating lobes. Our approach begins with a generation of sparse antenna ...
Abstract: This article presents a 7-bit, 1.15-GS/s, 2.6-bit/cycle asynchronous successive approximation register (SAR) analog-to-digital converter (ADC) that incorporates a comparator decision skip ...
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