Its use results in faster development, cleaner testbenches, and a modern software-oriented approach to validating FPGA and ASIC designs without replacing your existing simulator.
Beta: This SDK is supported for production use cases, but we do expect future releases to have some interface changes; see Interface stability. We are keen to hear feedback from you on these SDKs.
-n--nodes TEXT Path to Node CSV file with the filename as the Node Label -N--nodes-with-label TEXT Node Label followed by path to Node CSV file -r--relations TEXT Path to Relationship CSV file with ...
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