We’ve been following the open, royalty-free RISC-V ISA for a while. At first we read the specs, and then we saw RISC-V cores in microcontrollers, but now there’s a new board that offers enough ...

SiFive's oversubscribed series G round of financing suggests the industry's historical caution around the RISC-V architecture ...

Try these RISC-V SBCs instead of Raspberry Pi for your next project.

The RISC-V Summit North America, held on 22-23 October 2025 in Santa Clara, California, showcased the latest CPU cores featuring new vector processors, high-speed interfaces, and peripheral subsystems ...

Have you ever wondered if there’s a way to break free from the dominance of proprietary computing architectures like x86 and ARM? For decades, these platforms have dictated the rules of the game, ...

When the number two provider of CPU designs jumps on the RISC-V train, it is a significant milestone. The open-source RISC-V design is on a roll, displacing Arm in many SoC development plans. ARC and ...

The 2024 RISC-V Summit North America marked a significant milestone for the RISC-V community with the ratification of the RVA23 Profile. This event signifies a major step forward in the evolution of ...

Canonical announced today it's collaborating with SpacemiT (Hangzhou) Technology Co., Ltd. in an effort to make Ubuntu run on SpacemiT's RISC-V systems-on-chip (SoCs) that use the RVA23 profile. The ...

RISC-V, the open-standard Instruction Set Architecture (ISA) conceived by UC Berkeley developers in 2010, is going from strength to strength. The RISC in RISC-V stands for Reduced Instruction Set ...

RISC-V cores are beginning to show up in heterogeneous SoCs and packages, shifting from one-off standalone designs toward mainstream applications where they are used for everything from accelerators ...