Semiconductor Engineering

Universal Verification Methodology Running Out Of Steam

For the past decade or so, the Universal Verification Methodology (UVM) has been the de facto verification methodology supported by the entire EDA industry. But as chips become more heterogeneous, ...
EDN

SoC debug tool expands verification methods

The Verdi automated debug system for SoC design has expanded its verification interoperability by supporting the Universal Verification Methodogy (UVM). The software adds UVM source code and ...
Business Wire

MathWorks Speeds FPGA and ASIC Verification with Universal Verification Methodology (UVM) Support

NATICK, Mass.--(BUSINESS WIRE)--MathWorks today announced that HDL Verifier provides support for the Universal Verification Methodology (UVM) starting with Release 2019b, which is currently available.
techtimes

Revolutionizing Chip Testing Through Visionary Blueprints That Transform Semiconductor Verification

Prashanth Paladugu, a leading testbench architect at Micron, is transforming semiconductor design with his revolutionary approach to verification methodologies. "With the changing semiconductor ...
Electronic Design

Verification Techniques For FPGA Designs

With the increasing size and complexity of FPGA devices, there is a need for more efficient verification methods. Timing simulation can be the most revealing verification method; however, it is often ...
Semiconductor Engineering

How AI And Connected Workflows Will Close The Verification Bottleneck

For decades, verification has been the unsung hero of chip development—quietly catching bugs before they reach silicon. But as semiconductor complexity has skyrocketed, verification has turned into ...