Semiconductor Engineering sat down to discuss the verification of RISC-V processors with Pete Hardee, group director for product management at Cadence; Mike Eftimakis, vice president for strategy and ...

The open-source nature of RISC-V brings the benefits of a modular and royalty-free instruction set architecture (ISA) that eliminates licensing fees, can accelerate development, and fosters ...

The 2024 RISC-V Summit North America marked a significant milestone for the RISC-V community with the ratification of the RVA23 Profile. This event signifies a major step forward in the evolution of ...

The RISC-V Summit North America, held on 22-23 October 2025 in Santa Clara, California, showcased the latest CPU cores featuring new vector processors, high-speed interfaces, and peripheral subsystems ...

The chip was designed as part of Europe's broader effort to reduce reliance on non-European processor technologies.

When the number two provider of CPU designs jumps on the RISC-V train, it is a significant milestone. The open-source RISC-V design is on a roll, displacing Arm in many SoC development plans. ARC and ...

Forbes contributors publish independent expert analyses and insights. Dave Altavilla is a Tech Analyst covering chips, compute and AI. For decades, chip architectures have been dominated by a pair of ...

The Android Common Kernel is about to remove support for the RISC-V architecture. Android Common Kernel is Google’s fork of the upstream Linux kernel but with Android-specific additions. RISC-V is an ...

RISC-V, pronounced “risk five,” is a modern open-source instruction set architecture (ISA) based on reduced instruction set computer (RISC) principles. In simple terms, it’s like a blueprint that ...

Have you ever wondered if there’s a way to break free from the dominance of proprietary computing architectures like x86 and ARM? For decades, these platforms have dictated the rules of the game, ...