EDN

SystemVerilog assertions unify design and verification

The SystemVerilog standard is the result of an industry-wide effort to extend the Verilog language in a consistent way to include enhanced modeling and verification features. By adding verification ...
Design-Reuse

Introduction to SVA Assertions for Design Engineers

Assertions and Assertion-Based Verification (ABV) are a hot topic, but many engineering teams remain unfamiliar with the benefits that assertions bring to the design and verification process. This ...
Design-Reuse

Springer Publishes ARM-Synopsys Verification Methodology Manual for SystemVerilog

New ARM-Synopsys Book Provides Blueprint for System-on-Chip Verification Success Using SystemVerilog NEW YORK -- Sept. 21, 2005 -- Springer Science + Business Media, Inc., a major publisher of ...
Electronic Design

SystemVerilog Gains A Foothold In Verification

Indeed, designers have embraced SystemVerilog—it's by far the fastest growing design/verification language in the world today (Fig. 1). "The ability to do assertions is significantly improved in ...
Semiconductor Engineering

Easier Assertion Development And Debug With Simulation Replay

Assertions and assertion IP (AIP) are a core part of the register transfer level (RTL) verification environment for all modern chip development projects. Assertions can be considered as statements of ...
Electronic Design

SystemVerilog: The Complete Solution

The electronics industry is constantly challenged by the ever-growing design and verification requirements for complex chips. With the IEEE-Std 1800-2005 System-Verilog standard, the industry has a ...
Semiconductor Engineering

The Assertion Conundrum

It is well documented and widely agreed that assertions can provide a tremendous benefit to design and verification teams by reducing and even eliminating debug – but their use is still not ubiquitous ...