Semiconductor Engineering

Physical-Aware RTL Restructuring For SoC Cost Reduction

In modern SoC design, RTL hierarchy has to be manipulated throughout the entire design flow in order to accommodate different objectives at different stages of the design process. This becomes ...
Embedded

How virtual prototypes aid SoC hardware design

The world of the hardware design engineer has changed dramatically in recent years. Designers no longer sit and code RTL in isolation to meet a paper specification, and then wait for a hardware ...
EDN

SILICON ENGINEERING: SoC tools smooth SystemC-to-RTL flow

Mountain View, Calif. — Sonics Inc. claims a breakthrough in SystemC-based system on-chip modeling for new versions of its SonicsMX Smart Interconnect and SonicsStudio. The release is said to deliver ...
Dhaka Tribune

CVES launches course on RTL design, verification and VLSI synthesis

The American International University-Bangladesh (AIUB) inaugurated a new professional industry-focused course titled “RTL Design, Verification, Synthesis and PnR for Digital VLSI Design” on October 5 ...
Design-Reuse

Throttle IP Core Power Dissipation: Use RTL Power Analysis Early and Often

Because today’s System-On-Chip (SOC) designs contain millions of transistors, design engineers must treat power dissipation as an important design goal for IP blocks and not as just a data-sheet ...
Electronic Design

Navigating the Hardware-Software Interface in Chip Design

Designing the hardware-software interface. Dealing with "bytes enables" in RTL verification. Automating the HSI design process across the entire dev team. The hardware-software interface (HSI) holds ...
Semiconductor Engineering

Why SoC Designers Need Purpose-Built Semiconductor IP Catalog Tools

Semiconductor intellectual property (IP) management, reuse, and change tracking are essential for efficiently creating chip designs based on proven building blocks, reducing your time-to-market, and ...