EDN

Multiprocessing speeds IC physical verification

As manufacturing processes transition to more advanced technologies at 90nm and below, design signoff requirements become increasingly more rigorous and time-consuming. With each step to more advanced ...
Semiconductor Engineering

Interface DRC Can Streamline Chip-Level Interface Physical Verification

In most design companies, the chip-level physical implementation teams responsible for design floorplanning in place and route (P&R) environments also manage top-level physical verification from the ...
Electronic Design

Physical Verification in the Age of One Billion Transistors, One Thousand Design Rules, and Million Dollar Mask Sets

Physical-verification cycle time increases significantly with each new process generation. Rule-deck complexity contributes considerably to this effect. The number of design rules grows rapidly as ...
EDN

Cadence speeds IC physical verification

SANTA CRUZ, Calif. — Promising a “massively parallel” approach to IC design rule checking (DRC) and layout-versus-schematic (LVS), Cadence Design Systems this week is rolling out its Physical ...