EDN

Mentor Unveils FPGA Design-Flow Plans

Mentor Graphics is exploring the application of formal verification techniques in an FPGA design flow. Formal verification is recognized in the application-specific integrated circuit (ASIC) market as ...
EDN

FPGA synthesis can be a leverage point in your design flow

FPGA design starts are on the rise due to the lower startup costs and re-programmability that FPGA devices can provide. However, large, complex FPGA devices pose significant challenges to an FPGA ...
Electronic Design

Xilinx And Synopsys Collaborate On Tool Flow For Platform FPGAs

Time-saving verification tools have been added to an advanced tool flow for high-end FPGA design. The flow, a collaboration between Xilinx Inc. of San Jose and Synopsys Inc. of Mountain View, Calif., ...
Semiconductor Engineering

Why Your FPGA Synthesis Flow Requires Verification

When you think about it, logic synthesis is a vital but rather intimidating part of modern chip design. This process takes a high-level description of intended functionality, written in an RTL ...
Embedded

CPU plus FPGA design flow for software developers: A new tangible reality

Recently, Brian Bailey organized a round table that resulted in a two-part article called Supporting CPUs Plus FPGAs. The experts discussed the evolving reality of systems design based on FPGAs and ...
CU Boulder News & Events

FPGA Design for Embedded Systems Specialization

This online engineering specialization will help you gain proficiency in creating prototypes or products for a variety of applications using Field Programmable Gate Arrays (FPGAs). You will cover a ...
Electronic Design

Agilent FPGA design flow supports AXIe digitizer

June 23, 2014. Agilent Technologies Inc. has announced that the Agilent EEsof EDA W1462 SystemVue FPGA Architect now supports on-board FPGA design and simulation with the Agilent M9703A AXIe wideband ...
Design-Reuse

Actel Delivers Secure, Comprehensive Design Flow for Complex FPGA Development Using ARM7 Family Processor

Company's Libero IDE Also Bolsters Industry-Leading Static Timing Analysis and I/O Capabilities MOUNTAIN VIEW, Calif., Nov 02, 2005-- Actel Corporation (Nasdaq: ACTL) today unveiled significant new ...
Embedded

Tackle team-based FPGA design

You see them at almost every user seminar or industry trade show workshop: the Methodology Managers from XYZ Corporation, who describe the system they use to help the company make sense of the ...
Semiconductor Engineering

FPGA Design Tradeoffs Getting Tougher

FPGAs are getting larger, more complex, and significantly harder to verify and debug. In the past, FPGAs were considered a relatively quick and simple way to get to market before committing to the ...