Debugging design violations found by design rule checking (DRC) has always taken a significant share of the time needed to get a design to tapeout. And debug time only increases as the number and ...

(Intellectual property (IP) reuse, especially at the physical IP level, is a key component of the growing system-on-chip (SoC) ecosystem. However, with the increase in the amount and scope of custom ...

Santa Cruz, Calif. – Tanner EDA said it is providing a low-cost alternative to IC design rule checking with the introduction last week of HiPer Verify, the first in a line of layout and verification ...

Crunch time—that last six to eight weeks before tapeout. There’s always too much to do, and too little time. No one wants problems at this stage, because problems mean changes, and changes mean delays ...