Design-Reuse

Cadence and Denali Team Up to Enable Advanced DDR-PHY Methodology

Industry's Most Advanced DDR-PHY Solutions Achieved With Denali's Databahn PHY Architecture and CPF-Enabled Cadence SoC Encounter and Encounter Timing System SAN JOSE, CA -- May 31, 2007-- Cadence ...
EDN

Synopsys DesignWare DDR multiPHY IP Supports Six DDR Standards in a Single PHY

MOUNTAIN VIEW, Calif., April 7 /PRNewswire-FirstCall/ — Synopsys, Inc. (Nasdaq: SNPS), a world leader in software and IP for semiconductor design, verification and ...
Business Wire

Faraday Delivers DDR/LPDDR Combo PHY IP Solutions on UMC’s 22ULP and 14FFC

HSINCHU, Taiwan--(BUSINESS WIRE)--Faraday Technology Corporation (TWSE: 3035), a leading ASIC design and IP provider, today announced the availability of its DDR/LPDDR combo PHY, supporting from 3 rd ...
Electronic Design

Cadence and Denali Double-Team Advanced DDR-PHY Methodology

The combined resources of Cadence Design Systems and Denali Software have resulted in an advanced double-data-rate (DDR) PHY methodology based on Cadence’s Encounter digital IC design platform. The ...