Electronic Design

CMOS Circuit Design, Layout, and Simulation: Second Edition

As author R. Jacob “Jake” Baker points out in the preface to this comprehensive volume, CMOS technology has dominated the fabrication of ICs for 25 years, and is likely to dominate it for another 25 ...
Electronic Design

Layout-Dependent Modeling Boosts CMOS Gate Density

A layout-dependent circuit-design model from Toshiba helps boost gate density and improve cost-performance in next-generation 45-nm CMOS technology. More specifically, 45-nm CMOS gate density can be 2 ...
EDN

A Designer’s Guide to CMOS RF Models

In recent years we have begun to see references to “RF” CMOS processes and to “RF” models for those processes. This article will explore what the real meanings of such “RF” designations are, and what ...
Design-Reuse

Cryogenic CMOS design enabled by Semiwise

November 11, 2022 -- Semiwise has developed transistor SPICE models based on the GlobalFoundries (GF) 22FDX ® Platform that enable cryogenic CMOS design and verification. Using its patented ...
Hackaday

How CMOS Works: Some Final Words About CMOS

Finishing up on the topic of CMOS bus logic I am going to show a couple of families with unique properties that may come in handy one day. First up is a CMOS logic family AHC/AHCT that has one of the ...
EDN

IC Performance: Challenges in Layout with CMOS Technology Nodes

Editor’s note: I am pleased to bring you an important technical blog by Fernando Lavalle, a Ph.D. student at Texas A&M University and his colleague, Suraj Prakash, who have been working and studying ...
Semiconductor Engineering

Considerations for Porting a Bulk CMOS Design to FD-SOI

Technologists describe a straight port of an existing bulk CMOS design to FD-SOI at the same node, obtaining the value of fully depleted SOI for a modest redesign effort. November 16th, 2012 - By: ...