EDN

Altera’s Structured ASIC design flow now ITAR-compliant for military apps

Altera Corporation has announced that the U.S. Department of State has certified that the company's HardCopy II structured ASIC design and manufacturing flow is compliant with International Trade in ...
EDN

Focus is on the best ASIC design flow

System-on-programmable-chip technology has characteristics of both board-based design and ASIC-based system-on-a-chip ASIC design. The immediate attraction of SoPC is that, like a breadboard, the ...
Nasdaq

Synopsys DesignWare ARC Data Fusion IP Subsystem Incorporated by Himax in Their Artificial Intelligence WiseEye ASIC

Himax WiseEye ASIC platform is optimized for application developers deploying machine learning on battery-powered AIoT devices Synopsys DesignWare ARC Data Fusion IP Subsystem with audio software ...
Electronic Design

Flow Software Cuts ASIC Modelling Time

It is important to model an SoC well in advance to avoid costly over design or insufficient performance and to create a hardware emulation on which representative end user applications can be run. It ...
Semiconductor Engineering

Synopsys FPGA Platform: Enabling Faster Design, Verification and Debug of FPGAs

FPGA development teams are adopting ASIC-style design, verification and debug methodologies. Here are the necessary elements of such a flow. September 11th, 2019 - By: Synopsys Field programmable gate ...
Electronic Design

Carefully Weigh The Tradeoffs Of Cell-Based Vs. Structured ASICs

When all is said and done, the structured ASIC’s shorter development cycle may well be the deciding factor for your design team. With the emergence of 90-nm process technology, ASIC designers get to ...